It was so hard for me to do this counter for the first time but I could be able to do it with one of my friends who is a student doctor in electronic
I searched the web a lot for a sample code to help me provide a project for my lab
I couldn’t find any and I found so many forums and even yahoo answers that there were so many people frustrated of lack of internet content of any training and verilog sample
I am sure that many people are looking into it and I will provide my codes here with some instruction on each part
I will just put the codes there and will continue add instructions in the next days
The codes has already have some comments on them so that you may find some instructions from the comments

module TopFinal(Clk,Rst,SevenSeg,En1,En2,En3);
input           Clk;
input           Rst;
output  [6:0]       SevenSeg;
output              En1;
output              En2;
output              En3;     

reg [6:0]       SevenSeg;      
//initializing the 3 state enable
reg             En1;
reg             En2;
reg             En3;

  //our third party clock
reg             clkR;        
//our 2bit state
reg [1:0]       stateR;  
//our 20 bit counter   to generate third prty clock
reg [20:0]      cntR;

wire    [3:0]       temp3W;
wire    [3:0]       temp2W;
wire    [3:0]       temp1W;


wire    [6:0]       outTemp3W;
wire    [6:0]       outTemp2W;
wire    [6:0]       outTemp1W;


//conditioning the state
always @(posedge Clk) begin
    if(Rst)begin
        SevenSeg <= 0;
        En1 <= 0;
        En2 <= 0;
        En3 <= 0;
       
    end
    else
        case(stateR)
            0 : begin
                SevenSeg <= outTemp1W;
                En1 <= 1;
                En2 <= 0;
                En3 <= 0;            
            end
            1 : begin
                SevenSeg <= outTemp2W;
                En1 <= 0;
                En2 <= 1;
                En3 <= 0;            
            end
            2 : begin
                SevenSeg <= outTemp3W;
                En1 <= 0;
                En2 <= 0;
                En3 <= 1;            
            end        
        endcase
end

           
               
                    //creating the third party counter
always @(posedge Clk)
    begin
    if(Rst)
        cntR <= 0; 
    else
        cntR <= cntR +1;
    end
                   //generating more delayd clock
always @(posedge Clk)begin
    if(Rst)
        clkR <= 0;
    else         //our delaied clock
        clkR <= cntR[20];
end

always @(posedge cntR[10] or posedge Rst)begin
    if(Rst)
        stateR <= 0;
    else
        if (cntR[10])
            if(stateR == 2)
                stateR <= 0;
            else
                stateR <= stateR +1 ;
end


Counter cnt1(clkR,Rst,temp3W,temp2W,temp1W);
//seven segment 1
SevenSeg S1(temp1W,outTemp1W);
//seven segment 2
SevenSeg S2(temp2W,outTemp2W);
//seven segment 3
SevenSeg S3(temp3W,outTemp3W);




endmodule

the sevensegment

module SevenSeg(BCDinpt, segcntrl);
input [3:0] BCDinpt;
output reg[6:0] segcntrl;
always @(BCDinpt) begin
    case(BCDinpt)
          0: segcntrl = 7'b1111110;
          1: segcntrl = 7'b0110000;
          2: segcntrl = 7'b1101101;
          3: segcntrl = 7'b1111001;
          4: segcntrl = 7'b0110011;
          5: segcntrl = 7'b1011011;
          6: segcntrl = 7'b1011111;
          7: segcntrl = 7'b1110000;
          8: segcntrl = 7'b1111111;
          9: segcntrl = 7'b1111011;
          default: segcntrl = 7'b0000001;
    endcase  
end
   
endmodule

The Counter Part Module

module Counter(Clk,Rst,DataOut3,DataOut2,DataOut1)  ;    
   
    //initializing values
input           Clk;     //initialize clock as input
input           Rst;     //Initialize reset as input
//initialize outputs           
//100gan
output  [3:0]       DataOut3;
//dahgan
output  [3:0]       DataOut2;
//yeka
output  [3:0]       DataOut1;
//make the output as reg as they are using in the always block
reg     [3:0]       DataOut3;
reg     [3:0]       DataOut2;
reg     [3:0]       DataOut1;

reg [9:0]       cntR;     //initializing the counter       
//100gan temporary
reg [3:0]       data3R;      
//0 ta 99
reg [6:0]       decade1R;  


always @(posedge Clk or posedge Rst)
    begin
    if(Rst)     //if reset was enabled make the counter set to 0
        cntR <= 0; 
    else               //else the counter will incremented
        cntR <= cntR +1;
end

always @(posedge Clk or posedge Rst)begin
    if(Rst)begin
        decade1R<= 0;
        data3R  <= 0;
    end
    else                     //if the counter is greater than 899
        if(cntR > 899)begin
            data3R  <= 9;             //data3R is assigned to 9
            decade1R<= cntR-900;       // decade1R is assigned to cntR-900 let say cntR is 906 then  6 eill be assigned to decade1
        end
    else                         //inf cntR is greater than 799 then
        if(cntR > 799)begin
            data3R  <= 8;          //data3R is assigned to 8 because it is going to be mroe than 800
            decade1R<= cntR-800;
        end
    else                         //if cntR is greater than 699 then the data3R is going to equal to 7(sadgan msihe 7)
        if(cntR > 699)begin
            data3R  <= 7;
            decade1R<= cntR-700;
        end
    else                        //if cntR is greater than 599 data3R is going to be 6
        if(cntR > 599)begin
            data3R  <= 6;
            decade1R<= cntR-600;
        end
    else                            // if cntR is greater than 499 then the data3R is going to be equal to 5
        if(cntR > 499)begin
            data3R  <= 5;
            decade1R<= cntR-500;
        end
    else                             // if cntR is greater than 399 then the data3R is going to be 4
        if(cntR > 399)begin
            data3R  <= 4;
            decade1R<= cntR-400;
        end
    else
        if(cntR > 299)begin       // if cntR is greater than 299 then the data3R is going to be set to 3
            data3R  <= 3;
            decade1R<= cntR-300;
        end
    else
        if(cntR > 199)begin     // if the cntR is greater than 199 then the data3R will be equal to 2
            data3R  <= 2;
            decade1R<= cntR-200;
        end
    else                        //if cntr is rgeater than 99 then the data3R will be equalled to 1
        if(cntR > 99)begin
            data3R  <= 1;
            decade1R<= cntR-100;
        end
    else begin               // if none happened above the data3R is going to be set to 0
        data3R  <= 0;
        decade1R<= cntR;
    end
end




                                            // the following will check the decade1R
always @(posedge Clk or posedge Rst)begin
    if(Rst)begin
        DataOut1<= 0;
        DataOut2  <= 0;
    end
    else
        if(decade1R > 89)begin      // if the decade1R that is initialized if is grater than 89 then the following will be assigned
            DataOut2  <= 9;
            DataOut1<= decade1R-90;
        end
    else
        if(decade1R > 79)begin
            DataOut2  <= 8;
            DataOut1<= decade1R-80;
        end
    else
        if(decade1R > 69)begin
            DataOut2  <= 7;
            DataOut1<= decade1R-70;
        end
    else
        if(decade1R > 59)begin
            DataOut2  <= 6;
            DataOut1<= decade1R-60;
        end
    else
        if(decade1R > 49)begin
            DataOut2  <= 5;
            DataOut1<= decade1R-50;
        end
    else
        if(decade1R > 39)begin
            DataOut2  <= 4;
            DataOut1<= decade1R-40;
        end
    else
        if(decade1R > 29)begin
            DataOut2  <= 3;
            DataOut1<= decade1R-30;
        end
    else
        if(decade1R > 19)begin
            DataOut2  <= 2;
            DataOut1<= decade1R-20;
        end
    else
        if(decade1R > 9)begin
            DataOut2  <= 1;
            DataOut1  <= decade1R-10;
        end

    else begin
        DataOut2  <= 0;
        DataOut1<= decade1R;
    end
end


always @(posedge Clk or posedge Rst)begin
    if(Rst)
        DataOut3 <= 0;
    else
        DataOut3 <= data3R;
end
endmodule

Thanks

46 COMMENTS

LEAVE A REPLY

Please enter your comment!
Please enter your name here